This invention relates to a voltage comparator, which compares a plurality of input signals and provides an output signal corresponding to the voltage level difference of these input signals.
A prior art voltage comparator shown in FIG. 1, has a construction comprising an input circuit section 10 to receive a pair of input signals, a current-mirror circuit section 12 functioning as an active load with respect to the input circuit section 10, and an output circuit section 14. The input circuit section 10 includes a pair of PNP conductivity type signal input transistors, more particularly a noninverting input transistor 16 and an inverting input transistor 18. The collectors of these transistors 16 and 18 are connected to a ground potential line 20 which is further connected to ground G, and input signals applied to terminals 22, 24 are supplied to the bases of the transistors 16 and 18 respectively. The emitters of these signal input transistors 16 and 18 are connected through constant-current sources 26 and 28 to a high potential line, i.e., a power potential line 30.
The emitters of the transistors 16 and 18 mentioned above are also connected to the bases respectively of two transistors 34 and 36 which constitute a differential pair 32. The differential pair transistors 34 and 36 have the same conductivity type as the signal input transistors 16 and 18, i.e., PNP conductivity type. The emitters of the differential pair transistors 34 and 36 are commonly connected to each other and further connected through a constant-current source 38 to the power potential line 30. The collectors of the differential pair transistors 34 and 36 are connected to the ground potential line 20 through the aforementioned current-mirror circuit 12. The collector of the differential pair transistor 34 is also connected to the base of an output transistor 40 in the output circuit section 14. The output transistor 40 has its emitter grounded and its collector connected through a load resistor 42 to a power potential line 30. The collector of the output transistor is also directly connected to the output terminal 44.
In such a voltage comparator as described, when the voltage level V.sub.in(+) of the input signal supplied to the noninverting transistor 16 becomes higher than the voltage level V.sub.in(-) of the input signal supplied to the inverting input transistor 18 (these input signals being assumed to be either a positive voltage or 0 V), the noninverting input transistor 16 is in the "off" state. This has an effect of turning "off" the differential pair transistor 34 connected to the noninverting input transistor 16. At this time, no current flows to the base of the output transistor 40, so that the output transistor 40 is also in the "off" state, thus causing a high level voltage substantially the same as the power voltage V.sub.cc to appear at the output terminal 44 causing the output terminal 44 is become in the logic "HIGH" level. On the other hand, when the input voltage V.sub.in(+) to the noninverting input transistor 16 becomes lower than the input voltage V.sub.in(-) to the inverting input transistor 18, the noninverting input transistor 16 is turned "on", thus turning "on" the corresponding differential pair transistor 34 and output transistor 40. Thus, a low level voltage, i.e., substantially the ground potential, appears at the output terminal 44. In this way, an output signal, which changes in level between the ground potential level or logic "LOW" level and the power voltage level or logic "HIGH" level in accordance with the polarity of the and voltage level difference between a pair of input signals, is obtained.
Here, denoting the voltages of the noninverting and inverting input signals respectively by V.sub.in(+) and V.sub.in(-) as described above, they are related to the power voltage V.sub.cc as EQU V.sub.in(+) +V.sub.BE(16) +V.sub.BE(34) +V.sub.S =V.sub.cc ( 1)
and EQU V.sub.in(-) +V.sub.BE(18) +V.sub.BE(36) +V.sub.S =V.sub.cc ( 2)
where
V.sub.BE(16) : the base-emitter voltage across the noninverting input transistor 16; PA1 V.sub.BE(34) : the base-emitter voltage across the differential pair transistor 34 connected to the noninverting input transistor 16; PA1 V.sub.BE(18) : the base-emitter voltage across the inverting input transistor 18; PA1 V.sub.BE(36) : the base-emitter voltage across the differential pair transistor 36 connected to the inverting input transistor 18; and PA1 V.sub.S : the voltage drop across the constant-current source 38 connected between the junction of the emitter of the differential pair transistors 34 and 36 and the power potential line 30.
Since the input signal voltages V.sub.in(+) and V.sub.in(-) are such that: EQU V.sub.in(+) .gtoreq.0 (3)
and EQU V.sub.in(-) .gtoreq.0, (4)
by setting EQU V.sub.BE(16) =V.sub.BE(18) =V.sub.BE(34) =V.sub.BE(36) =V.sub.BE,
from the equations 1 and 2, there is obtained EQU V.sub.cc =2V.sub.BE +V.sub.S ( 5)
Actually, the base-emitter voltage V.sub.BE across the individual transistors is 0.7 V and the voltage drop V.sub.S across the constant-current source 38 is 0.1 V, by substituting these values into the equation 5 EQU V.sub.cc .gtoreq.1.5 (6)
Thus, it will be seen that for the operation of the prior art voltage comparator a voltage of at least more than 1.5 V is necessary as the power voltage.
Since according to Equation 6 a power voltage V.sub.cc as large as 1.5 V generates an ineffective voltage drop, according to Equations 1 and 2 a power voltage V.sub.cc set for instance at 2 V restricts allowable voltage amplitudes of the input signals restricted to a narrow range between 0 and 0.5 V.